Language Breakdown
Lines of code distribution across 9 owned repositories
I-Shaped Developer
I-shapedSpecialist — deep expertise in VHDL
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Repos
10
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0
Growth
+18%
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A fully hardware-based real-time audio spectrum analyzer on the Nexys4 DDR (Xilinx Artix-7 XC7A100T). An analog audio signal is digitized by the onboard XADC, processed through a 1024-point fixed-point FFT pipeline, and rendered as a live color bar chart on a VGA monitor — all in RTL Verilog, no processor involved.
A complete PS/2 keyboard interface that receives keystrokes, decodes scan codes, converts them to ASCII, and transmits them over UART. Designed and simulated using Xilinx Vivado.
A fully parameterizable SPI (Serial Peripheral Interface) Master/Slave implementation in Verilog, supporting all 4 CPOL/CPHA modes. Designed and simulated using Xilinx Vivado.
A fully parameterizable UART (Universal Asynchronous Receiver Transmitter) implemented in Verilog. Designed and simulated using Xilinx Vivado. Supports configurable data bits, stop bit length, and baud rate.
Open Source Impact
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